Below are instructions on how to simulate the VHDL implementation of Ben Eater’s computer. They also double as a general introduction to ModelSim.
Running the simulation
1) Get ModelSim. It’s free software.
2) Download the VHDL code from Github.
3) Open ModelSim, and create a new project.
As part of the Homebrew Computer Project, I have been exploring other CPU architectures and their implementations in order to broaden my understanding of CPU design.
An awesome one that I came across was Ben Eater’s 8-bit computer. It is well documented through a series of videos on Youtube and also on his blog. The architecture is simple which allows you to get a firm understanding of all its components.
Since it is a known working design, I saw it as the perfect opportunity to practice implementing a CPU in VHDL.
Next in line in the awesome tutorial series from Nandland was VGA. I didn’t have a VGA connector for my FPGA, but wondered if I could jury-rig something with what I had on hand.
The wiring diagram below from Grant Seale’s Multicomp gave me a very good idea on how to go about it.
In the Nandland tutorial (image below), three signals are used per channel instead of two so my setup reflects that.
I had five 1Kohm resistors on hand, enough to control one channel. I used two of them in parallel to get the 500 ohms (close enough to 549), two in series to get the 2K ohms, and one on its own for the 1K ohms. Jumper wires were used to connect to the pins (red, green, blue, hsync, vsync). Luckily, all the ground pins were in-line (and the random pin in-between was an unused pin) so I just tied the whole line to ground using one wire (instead of several jumper wires). Here is the final masterpiece:
And the overall setup:
For the homebrew computer, I will need to implement SPI and I2C support to allow the FPGA to communicate with the LCD screen and ADC. To get an idea of how to go about this, I turned to tutorials uploaded on Youtube. But before getting in deep, I started by learning a simpler protocol, asynchronous serial communication.
I chose to use VHDL to program the FPGA because it is closer to a schematic representation than Verilog. Verilog seems (to me) like learning a new programming language whereas VHDL is more like describing the circuit.
For example, take the construction of a full adder. Here is a video of the structure generated by my code below: